Fire fighting and control simulator

ABSTRACT

A simulator for training in fire fighting and control employing a plurality of modules arranged in a matrix of adjacent modules, each module employing a fire simulation unit, such as an electric lamp or gas burner energized to manually &#39;&#39;&#39;&#39;on&#39;&#39;&#39;&#39; condition with sensor and trigger circuit means for progressively deactivating the simulation units, time delay holding circuit means for maintaining deactivation of said units as the simulated fire is extinguished and interlocking logic circuitry with additional time delay means for limiting reflash capability of each &#39;&#39;&#39;&#39;off&#39;&#39;&#39;&#39; condition module fire simulation unit dependent upon the time duration of its exposure to &#39;&#39;&#39;&#39;on&#39;&#39;&#39;&#39; condition simulator units in adjacent modules.

United States Patent Swiatosz et al.

[ 1 July 11,1972

154] FIRE FIGHTING AND CONTROL SIMULATOR [72] Inventors: Edmund Swiatmz,Maitland; Walter S.

Chambers, Winter Park, both of Fla.

[22] Filed: April 26, 1971 [21] Appl. No.: 137,293

[52] US. CL ..3S/10, 169/1 R [51] Int. Cl. ..G09b 9/00 [58]FieldoiSeai-eh ..35/l0, l3;235/184,185; 169/1 R, 1A,2R

[56] References Cited UNITED STATES PATENTS 3,359,652 12/1967 Prosser eta1. ..35/l0 i 4" l i. 1

3,451,147 6/1969 Mehligetal. ..35/l3 3,l56,908 11/1964 Kopanetal...l69/1RX Pfimaq' Examiner-Wm. H. Grieb Attorney-Richard S. Sciascia andJohn W. Pease [57] ABSTRACT A simulator for training in fire fightingand control employing a plurality of modules arranged in a matrix ofadjacent modules, each module employing a tire simulation unit. such asan electric lamp or gas burner energized to manually on" condition withsensor and trigger circuit means for progressively deactivating thesimulation units, time delay holding circuit means for maintainingdeactivation of said units as the simulated fire is extinguished andinterlocking logic circuitry with additional time delay means forlimiting reflash capability of each 011' condition module firesimulation unit dependent upon the time duration of its exposure to on"condition simulator units in adjacent modules.

its as assist! LOGlC SYSTEM ClRCUITRY L MATRIX SENSORS AND INDICATORSLOGIC SYSTEM CIRCUITRY INVENTORS EDMUND SWIATOSZ WALTER S. CHAMBERS ATTORNE Y P'A'TENTEDJuL n ma 3, 75,343

sum a nr 3 INTERCONNECT LINES l l J c l TERMINATION MODULEI INDICATOR,|8 SENSOR AND f PowER LOGIC SOURCE WALTER S. CHAMBERS M M L/,,/

ATTORNEY PATENTEnJuL 11 m2 3. 675.343

sum 3 or 3 I4 z q..-.

INVENTORS EDMUND SWIATOSZ WALTER S. CHAMBERS ATTORNEY FIRE FIGHTING ANDCONTROL SIMULATOR STATEMENT OF GOVERNMENT INTEREST The inventiondescribed herein may be manufactured and used by or for the Governmentof the United States of America for governmental purposes without thepayment of any royalties thereon or therefor.

CROSS-REFERENCE TO RELATED APPLICATION This invention is an improvementto the related application of Hanns H. Wolff, Ser. No. 122,399, filedMar. 9, I971 titled FIRE FIGHTING TRAINER.

BACKGROUND OF THE INVENTION This invention relates to the field ofsimulators and more articularly to a simulator for instruction in theart of fighting and controlling oil spread fires.

In the past, fire fighting schools have used a diesel fuel oil as a firesource in the training of students in the technique of timed progressiveextinguishing of fires. One disadvantage of the use of oil spreadnatural fires is the volume of black smoke and resulting pollution ofthe air. A further disadvantage is the hazard of refiash and resultantenvelopment of the fire fighter particularly in fighting fires inenclosures. To avoid the above mentioned disadvantages, a system of firesimulation modules of gas or light units responsive to suitable sensormeans has been developed by Dr. Hans H. Wolff and disclosed in the abovementioned cross-referenced patent application, Ser. No. 122,399. In theabove mentioned system there is provided the capability of simulation ofan actual fire and progressive extinguishing of the fire to avoidrefiash resulting from inadequate time duration of sensor activation foreach fire simulation unit in a matrix of simulation modules, as well asa fixed time delay means to simulate refiash of the fire if allsimulation units are not extinguished in the time period of the fixedtime delay.

More realistic simulation of proper procedure in the extinguishment of afire would be provided if each simulation unit was responsive to theactual on" off condition of adjacent units in the simulation of reflashpotential of the fire.

SUMMARY OF THE INVENTION To provide a further realistic feature insimulation of actual fire conditions, the present invention is directedto a matrix of fire simulation modules wherein in addition to sensoractuated fire simulation units with associated deactivation and holdingcircuit means, there is also combined interlocking logic circuitryincluding gate, trigger and additional time delay means to permit andinhibit refiash capability in each off condition module fire simulationunit in dependence upon the time duration of its exposure to on"condition simulator units in adjaccnt modules.

DESCRIPTION OF THE DRAWINGS FIG. I illustrated diagrammatically a matrixof interconnected fire simulator units and associated sensors connectedto a logic system circuitry and embodying the invention,

FIG. 2 illustrates diagrammatically an integrated arrangement of modulesincorporated in the logic system circuitry of FIG. 1,

FIG. 3 is a circuit diagram of one of the identical modules of FIG. 1and its interlocking logic circuitry and also shows portions of adjacentinterconnected modules, each module being associated with a lightresponsive sensor and associated light element, and

FIG. 4 shows diagrammatically a modification of FIG. 3 utilizing a gasburner and associated sensor in place of the light and light responsivesensor of FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. I, the areacovered by the simulated fire is shown by the dotted outline and isrepresented by a matrix of pairs of sensors S and lights L. The numberof nodes in the matrix is arbitrary and depends upon the total area ofthe fire desired. The logic system circuitry indicated at 12 comprises aplurality of interconnected identical logic modules I4, as shown in FIG.2, each module being connected by cable means 16 (FIG. I) to serve asensor S and light L pair. Power for energizing the lights L is obtainedfrom a suitable power source 18 (FIG. 2) via suitable connecting means20. The spacing of the nodes, i.e., the pairs of lights and sensors,depends upon the time constants of the logic circuitry in accordancewith the degree of realism desired for the simulator.

To control the operation of the lights L in accordance with realisticextinguishing of a fire, each module 14 of the logic system is providedwith means for initially activating the lights L to normally on"condition, deactivating means for extinguishing each light progressivelyresponsive to action of its associated sensor, holding circuit means forholding the light in "off" condition for a selected period of time andinterlocking circuitry for permitting and inhibiting refiash capabilityof each "011 condition light in dependence upon the light conditions inadjacent areas of the simulated fire.

A suitable logic module circuit 14 is shown in FIG. 3. For convenienceof the drawing and description, the lights I. and sensors 5 have beenshown within the module 14 and within the portions shown of the logiccircuit of adjacent modules.

Referring to FIG. 3, in module I4 is provided a light L1 and lightresponsive sensor S1. Activating means in the form of a light inverterdriver circuit 22 connected to a source of power indicated is providedto activate the light LI to normally on condition. To provide fordeactivating the light Ll to off condition responsive to actuation ofthe Sensor SI, a triggering circuit 24 is provided. The triggeringcircuit 24 is connected to receive the output of sensor S1 through lines26 and 28 and to pass a deactivating signal to the inverter driver 22via line 30, OR gate 32 and lines 34 and 36. Thus, when the sensor S1 isactivated by a light source (not shown) simulating the use of a firehose (not shown) the light LI is extinguished simulating theextinguishing of a portion of the overall fire area.

Normally an area offire will remain extinguished if the area is hosedfor a selected period of time. To simulate this condition, time delaymeans is provided in the form of a capacitor and resistance circuit 38,a triggering circuit 40 and a flip-flop 42. The capacitor and resistivecircuit 38 is connected by line 44 to receive the output of the triggercircuit 24. After a time delay necessary to charge the capacitor ofcircuit 38, its output is passed on line 46 to the trigger circuit 40which via a line 48 sets the flip-flop 42 to pass a signal on a line 50through OR gate 32 and lines 34 and 36 to the driver 22 to maintain thelight L1 in oft condition. The light LI then remains in off conditionunless there is such delay in extinguishing the lights of adjacent nodesof the light matrix as to cause a refiash effect and re-ignition oflight L1. The additional interlocking logic circuitry for accomplishingthis efi'ect will now be described.

This interlocking circuitry as shown in FIG. 3 includes gate, triggerand additional time delay means. More specifically, there is provided inaccordance with the invention an exclusive OR gate 52, an AND gate 54, acharging capacitor 56, a trigger circuit 58, AND gates 60 and 62, an ORgate 64 with inverter at one input terminal as indicated and an OR gate66. The output of the exclusive OR gate 52 is passed on a line 68 to ANDgate 54, thence on a line 70 to the charging capacitor 56, thence on aline 72 to the trigger circuit 58 and thence on lines 74, 76, and 78 tothe AND gates 60 and 62. In the module I4 is provided a portion of logiccircuitry identified by the elements 80, 82, 84, 86, 88, and which areidentical to the respective elements 52, 54, 56, 58. 60, and 62 andconnected in the same manner described above.

It is to be understood that all of the several modules connected to thelights and sensors are identical. Therefore, a complete showing of allthe modules is unnecessary. However, in order to explain theinterconnecting logic circuitry of modules representing adjacent nodesof the matrix and thereafter to explain the overall operation of thesimulator, there is shown to the left of the module 14 and below themodule 14, a portion of each of the adjacent modules. This, to the leftof the module 14 are shown the elements 82, L2, 222, 264, 232, 224, 238,240, 242, and 266 corresponding to the elements S1, L1, 22, 64, 32, 24,38, 40, 42, and 66 of the module 14. Below the module 14 are shown theelements S3, L3, 322, 364, 332, 324, 338, 340, 342, and 366 againcorresponding to the elements S1, L1, 22, 64, 32, 24, 38, 40, 42, and 66of module 14.

Considering now the interconnection between adjacent modules, theexclusive OR gate 52 of module 14 is connected to function in accordancewith the condition of the lights L1 and L2. If the lights L1 and L2 arein the same state, i.e., both on or both off," there is no outputsignal. However, if they are in different conditions, one on and theother "off," an output signal is developed. Thus, one input to the gate52 is obtained via lines 34, 92, 94, 96, 98, 100, and 102 from theoutput signal of OR gate 32 determining the condition of light L1,Another input to exclusive OR gate 52 is obtained via lines 104, 106,108, 110, and 112 from OR gate 232.

The output of exclusive OR gate 52 is passed on line 68 as one input toAND gate 54. A second input to AND gate 54 is provided from inverter ORgate 264 via a line 114 and a third input to the AND gate 54 is providedfrom inverter OR gate 64 via lines 116, 117, 118, and 120. AND gate 54provides an output signal only when all three input lines are energized.AND gate 60 is provided with an input via lines 104, 106, 108, 110, anda line 122. AND gate 62 is provided with an input via lines 34, 92, 94,96, 98, 100 and a line 124. The output of AND gate 60 is passed on aline 126 to OR gate 266 and thence on a line 128 to flip-flop 242 toreset flip-flop 242 and turn light L2 to on" condition. Similarly, theoutput of AND gate 62 is passed on a line 130 to OR gate 66 and thenceon a line 132 to reset flip-flop 42 and turn light Ll to "on condi- Theinterconnection of module 14 to the module next adjacent below it isaccomplished in the same manner as described above for module 14 and itsleft adjacent module. Thus. in module 14 the exclusive OR gate 80 isconnected to the signal source for light Ll via lines 34, 92, 94, 96,132, and 134 and is connected to the signal source for light L3 vialines 136, 138, 140, and 142. The output of exclusive OR gate 80 ispassed through AND gate 82, capacitor-resistor circuit 84 and triggercircuit 86 to the AND gates 88 and 90 via lines 144, 146, 148, 150, 152,and 154. The output of AND gate 90 is passed on line 156 to OR gate 66and the output of AND gate 88 is passed on line 158 to OR gate 366. ANDgate 82 is connected to inverter OR gate 64 via lines 116, 117 and 160,and to inverter OR gate 364 via lines 162 and 164. The one terminal ofAND gate 90 is connected by line 166 to line 132 to condition gate 90 tothe condition of light L1. The one terminal of AND gate 88 is connectedby line 168 to line 140 to condition gate 88 to the condition of lightL3. Sensor S1 is connected to inverter OR gate 64 via lines 26 and 170.Sensor 52 is connected to inverter OR gate 264 via lines 172 and 174 andto OR gate 232 via lines 172, 176, trigger 224 and lines 178 and 179.Sensor S2 is connected to flip-flop 242 via lines 172 and 176, trigger224, line 178, capacitor-resistor circuit 238, line 180, trigger 240,and line 182 to set the flip-flop 242 and thence by line 184 to OR gate232. Sensor S3 is connected to flip-flop 342 via line 186, line 187,trigger 324, line 188, capacitor resistor circuit 338, line 190, trigger340, and line 192 and thence via line 194 to OR gate 332. Sensor 53 isconnected to the inverter terminal indicated of OR gate 364 via lines186 and 196, and to OR gate 332 via lines 186, 187, trigger 324, line188 and line 185.

OPERATION Considering operation of the simulator, as shown in FIG. 1, asensor and light are located in each area of adjacent areas forming amatrix of sensor and light pairs to represent adjacent areas of anoverall fire area. The lights L1. L2 and L3 as shown in FIG. 2 are innormally on" condition representing fire condition. Each light isinitially extinguished by activation of its associated sensor bydirecting a ray of light on the sensor, such action representing hosingof that area of the fire.

Thus, activation of sensor S2, for example, produces an output signalvia trigger 224 and OR gate 232 to act upon the inverter driver 222 andextinguish light L2. If the activation of sensor S2 is immediatelyremoved, the loss of signal to driver 222 will reignite light L2simulating the condition of reflash. However, if activation of sensor 82continues for a time period dependent upon the time constant of thecapacitor-resistor circuit 238, the flip-flop 242 will be activated toset condition and an output signal thereof via OR gate 232 will maintainan input signal to driver 222 and thereby maintain light L2 extinguished. This condition will prevail until the flip-flop 242 is reset bya signal on line 128 from OR gate 266, as will be hereinafter explained.

If the simulated hosing operation is now transferred to the tire arearepresented by sensor S1 and light L1, sensor S] will be activated,producing a signal via trigger 24 and OR gate 32 to energize inverterdriver 22 and extinguish light L1. If the simulated hosing of sensor S1is immediately removed, the light L1 will reignite indicatinginsufficient time of hosing and resultant reflash of light Ll. If thehosing is continued for a period of time dependent upon the delay timeconstant of capacitor-resistor circuit 38, flip-flop 42 will be set viatrigger 40 and a holding output signal will be applied to the inverterdriver 22 via the OR gate 32 from flip-flop 42.

Transferring the simulated operation to the fire area represented bysensor S3 and light L3, activation of sensor 53 immediately extinguisheslight L3 via the operation of trigger 324, OR gate 332 and inverterdriver 322. Continued hosing of the area for a selected time periodavoids reflash by setting the flip-flop 342 via capacitor-resistorcircuit 338 and trigger 340 such that the output from the set flip-flop342 is applied through OR gate 332 to maintain inverter driver 322energized and light L3 extinguished.

We have described thus far the means for simulation of fire in adjacentfire areas, the means for progressively extinguishing adjacent fireareas. and the time delay holding circuit means for hosing a specificarea a sufficient time to prevent reflash from the heat of theindividual area being extinguished. There is, however, under actual fireconditions the risk of reignition of one fire area due to an overtimeexposure thereof to an adjacent fire area which is in ignited condition.To simulate this effect and teach the need for timely extinguishing ofadjacent fire areas, the interlocking logic circuitry with additionaltime delay means is provided for application. Thus, assuming the fire inthe area of light L2 is extinguished properly, the flip llop 242 is inset condition, and that the sensor S1 is being activated to extinguishthe light Ll, the inputs to AND gate 54 are then as follows. Line 106 isreceiving a signal from flip-flop 242 and passing a signal through gate264 to line 114. There is no output from inverter gate 64 and hence nosignal on input line of AND gate 54. There is also no signal on inputline 68 to AND gate 54 because both lights L2 and L1 are in the samecondition and the exclusive OR gate requires a difference in inputsignals to develop an output signal. AND gate 54 requires an input onall three input lines to provide an output signal and hence there is nooutput signal on line 70.

Assuming that activation of S1 is continued until flip-flop 42 isactivated to set condition, the conditions are then as follows. Line 114remains carrying an input signal to AND gate 54. Line 68 from OR gate 52carries no input signal because lights L2 and L1 are in the samecondition, i.e., extinguished. Line 120 to AND gate 54 is carrying aninput signal from inverter OR gate 64 via lines 116, 117, and 118. Thereis still no output from AND gate 54 because there is no input signal online 68 to AND gate 54.

There is now a time period in which the fire in the area of light L3must be properly extinguished to avoid a reflash of the fire area oflight L1. If one does not proceed expeditiously to extinguish light L3,the following conditions prevail with respect to the inputs to AND gate82. Line 160 via line 117 carries a signal from the output of OR gate64. Line 144 carries a Signal from exclusive OR gate 80 because light L!is extinguished and light L3 is on." In other words, one input to ORgate 80 is energized via lines 92, 94, 96, 132, and 134. The other inputline 142 to OR gate 80 is passing no signal because there is no signalon line 138 connected to line 142 via line 140. The third input line 164to AND gate 82 is carrying a signal from OR gate 364 from line 162. Allthree inputs to AND gate 82 being energized, the AND gate 82 will aftera time delay pass an input to AND gate 90 via line 146,capacitor-resistor circuit 84, line 148, trigger 86 and lines 150 and154. The other input to AND gate 90, line 166 is also energized vialines 132, 96, and 94, 92 and 34 from OR gate 32, thereby providing anoutput on line 156 from AND gate 90 and an input to flip-flop 42 via ORgate 66 and line 132. This signal resets flip-flop 42 and cuts off theholding signal activating driver 22 via line 50, OR gate 32 and lines 34and 36. Light L1 is thereby reignited simulating reflash condition.

However, if light L3 is properly extinguished within the time periodestablished by the capacitor-resistor circuit 84, then lights Li and L3will be in the same condition and there will be no further output fromOR gate 80 and reflash of light Ll will be avoided. The same simulationof reflash is obtained for overtime exposure of an extinguished firearea to any other non-extinguished area. For example, if the fire areasL2 and L3 had been extinguished and there was undue delay inextinguishing the area of light Ll, then AND gate 88 would be broughtinto operation to reset flip-flop 342 via OR gate 366 and light L3 wouldbe caused to flash back to on condition.

In summary the above described system simulates all of thecharacteristics of an actual fire requiring sufficient time of hosingeach fire area to prevent immediate reflash and at the same time anexpeditious movement from one area to another to prevent reflash due toovertime exposure of an extinguished area to an adjacent unextinguishedarea which also would result in refiash.

It is to be understood that various modifications and substitutions canbe employed in the above described circuitry without departing from thebasic invention involving the provision of the above described interlocklogic system. Thus, for example, as shown in FIG. 4, one may employ agas burner 400, relay controlled valve 402 and relay 404 in place of thelamp L1. The burner is supplied with gas from a source indicated by thearrow 406 and the valve 402 is operated to on condition by the relay 404responsive to the output of the driver 22. No modification is requiredin the remainder of the circuitry previously described. The valve 402could alternatively be motorized instead of relay operated. Also, inplace of the sensor S1, one may employ a water responsive vane typeswitch as indicated by a vane 408 connected to a microswitch 410supplied from a source of electrical energy indicated for providing anoutput to the inverter terminal of the inverter OR gate 64. One couldalso employ as the sensor a tank (not shown) for accumulating a quantityof water to activate the micro-switch when the water reaches apredetermined weight. The tank (not shown) would have a continuousbleed-off to reset the switch when the water is not being accumulated.

I claim:

1. A fire simulator for training in fire fighting and controlcomprising:

a. a plurality of fire simulation units and a plurality of sensor meansfor arrangement in a matrix of pairs of fire simulation unit andassociated sensor,

b. a logic system of electrically interconnected modules connected tosaid sensors and simulation units, each of said modules including c.activating means for connecting said units to a source of energy fornormally fon" condition, d. deactivating means including a triggerclrcult connected to said activating means and responsive to activationof said sensor for deactivating said activating means and therebyextinguishing said fire simulation unit,

e. a holding circuit including time delay means for holding said unit inofF' condition responsive to maintaining said sensor activated for aselected time period, and time delay interlocking logic circuitry meansincluding a plurality of interlocking logic circuits connecting eachmodule to its adjacent modules to permit and inhibit reflash capabilityin each off" condition fire simulation unit in dependence upon the timeduration of its exposure to on condition simulator units in adjacentmodules.

Apparatus according to claim I,

said simulator units comprising electric lamps, and

said sensor comprising a photoelectric cell.

Apparatus according to claim 1,

said simulation units comprising a gas valve means, pilot light andburner, and

b. said sensor means comprising a water pressure responsive actuatingmeans for said gas valve means.

4. Apparatus according to claim 1,

a. said activating means comprising an inverter driver circuit,

b. said deactivating means including a trigger circuit, a first OR gateand inverter driver circuit,

c. said trigger circuit being connected to said sensor for passing anoutput signal through said first OR gate to said driver circuit tocondition said simulation unit to "off condition responsive to actuationof said sensor.

5. Apparatus according to claim 4,

a. said holding circuit including a capacitor-resistor circuit connectedto said trigger circuit,

b. a second trigger circuit connected to receive an output from saidcapacitor-resistor circuit after a time delay necessary to charge thecapacitor of said circuit,

c. a flip-flop circuit connected to said OR gate, and

d. a trigger circuit connected to set said flip-flop to on" condition topass a signal to said OR gate responsive to an output signal from saidcapacitor-resistor circuit.

6. Apparatus according to claim 5,

a. each of said interlocking logic circuits including b. an exclusive ORgate having two inputs connected respectively to the output of saidfirst OR gate of its unit module and to the output of said first OR gateof a next adjacent unit module to sense the relationship of identical ordifferent light conditions in adjacent modules and to provide an outputsignal only when said conditions are different,

c. an inverter OR gate having an inverter input terminal connected tosaid sensor and another input terminal connected to the output of saidfirst OR gate,

d. a triple input AND gate having one input connected to receive theoutput of said exclusive OR gate and its remaining input terminalsconnected respectively to the outputs of said inverter OR gate in itsunit module and in an adjacent unit module, said AND gate providing anoutput signal only when all three inputs are energized,

e. a reset AND gate and an additional time delay means including acapacitor circuit and a trigger circuit connected to receive the outputof said triple input AND gate and provide one input to said reset ANDgate, the other input to said reset AND gate being obtained from theoutput of said inverter OR gate, and

f. a reset OR gate connected to receive the outputs of the reset ANDgate in its unit module and the reset AND gate in each adjacent unitmodule.

1. A fire simulator for training in fire fighting and controlcomprising: a. a plurality of fire simulation units and a plurality ofsensor means for arrangement in a matrix of pairs of fire simulationunit and associated sensor, b. a logic system of electricallyinterconnected modules connected to said sensors and simulation units,each of said modules including c. activating means for connecting saidunits to a source of energy for normally ''''on'''' condition, d.deactivating means including a trigger circuit connected to saidactivating means and responsive to activation of said sensor fordeactivating said activating means and thereby extinguishing said firesimulation unit, e. a holding circuit including time delay means forholding said unit in ''''off'''' condition responsive to maintainingsaid sensor activated for a selected time period, and f. time delayinterlocking logic circuitry means including a plurality of interlockinglogic circuits connecting each module to its adjacent modules to permitand inhibit reflash capability in each ''''off'''' condition firesimulation unit in dependence upon the time duration of its exposure to''''on'''' condition simulator units in adjacent modules.
 2. Apparatusaccording to claim 1, a. said simulator units comprising electric lamps,and b. said sensor comprising a photoelectric cell.
 3. Apparatusaccording to claim 1, a. said simulation units comprising a gas valvemeans, pilot light and burner, and b. said sensor means comprising awater pressure responsive actuating means for said gas valve means. 4.Apparatus according to claim 1, a. said activating means comprising aninverter driver circuit, b. said deactivating means including a triggercircuit, a first OR gate and inverter driver circuit, c. said triggercircuit being connected to said sensor for passing an output signalthrough said first OR gate to said drIver circuit to condition saidsimulation unit to ''''off'''' condition responsive to actuation of saidsensor.
 5. Apparatus according to claim 4, a. said holding circuitincluding a capacitor-resistor circuit connected to said triggercircuit, b. a second trigger circuit connected to receive an output fromsaid capacitor-resistor circuit after a time delay necessary to chargethe capacitor of said circuit, c. a flip-flop circuit connected to saidOR gate, and d. a trigger circuit connected to set said flip-flop to''''on'''' condition to pass a signal to said OR gate responsive to anoutput signal from said capacitor-resistor circuit.
 6. Apparatusaccording to claim 5, a. each of said interlocking logic circuitsincluding b. an exclusive OR gate having two inputs connectedrespectively to the output of said first OR gate of its unit module andto the output of said first OR gate of a next adjacent unit module tosense the relationship of identical or different light conditions inadjacent modules and to provide an output signal only when saidconditions are different, c. an inverter OR gate having an inverterinput terminal connected to said sensor and another input terminalconnected to the output of said first OR gate, d. a triple input ANDgate having one input connected to receive the output of said exclusiveOR gate and its remaining input terminals connected respectively to theoutputs of said inverter OR gate in its unit module and in an adjacentunit module, said AND gate providing an output signal only when allthree inputs are energized, e. a reset AND gate and an additional timedelay means including a capacitor circuit and a trigger circuitconnected to receive the output of said triple input AND gate andprovide one input to said reset AND gate, the other input to said resetAND gate being obtained from the output of said inverter OR gate, and f.a reset OR gate connected to receive the outputs of the reset AND gatein its unit module and the reset AND gate in each adjacent unit module.